1. Field of the Invention
The present invention relates to a circuit synthesizing method for LSIs and other types of integrated circuit devices and a circuit synthesizing device therefor, and more particularly to a circuit synthesizing method for enabling to synthesize a circuit with a small circuit area and to a circuit synthesizing device therefor.
2. Description of the Related Art
In recent years, LSIs in general have become larger in size and more complex in structure, leading to increasing demand for a system that can automate logical design in order to achieve higher efficiency in LSI design. As a means of realizing automated circuit design, a circuit synthesizing device has been provided for describing the behavior of a circuit using the hardware description language and then synthesizing a desired circuit according to the description that has been input.
In general, the design levels of circuit synthesizing devices consist of three types: behavior, RTL (Register Transfer Level), and logic.
The behavior level is the same level as considering an algorithm using the programming language, which is a design level for defining xe2x80x9cwhatxe2x80x9d behaves xe2x80x9chow.xe2x80x9d In behavior synthesis, scheduling is performed to determine the clock cycle and the procedure in which an operation is to be carried out on a behavior description. As a result of this scheduling, registers and functional units are allocated to variables and registers (i.e., binding) as necessary, and a state machine part for controlling the sequence of the operation is generated (i.e., state generation).
The RTL is a level one order below the behavior level. This level defines an architecture using such components as registers, functional units, and a state machine part, and clarifies the behaviors of individual clock cycles. Actions in RTL synthesis include inferring registers from descriptions, optimizing the operational sequence, and allocating resources.
The logic level is the lowest level, which expresses a design circuit using Boolean expressions, ASIC net lists, and so forth. The term xe2x80x9clogic synthesisxe2x80x9d usually refers to synthesis at the logic level.
It should be noted here that a functional unit very often has a large circuit area. When synthesizing a circuit, therefore, sharing of a functional unit that is not used simultaneously is desirable so that the area of a logic-synthesized circuit can be prevented from becoming too large.
As an example, we will take the case in which the following is input into a circuit synthesizing device as a behavior description:
unsigned a1(0:2),b1(0:2),c1(0:4);
unsigned a2(0:3),b2(0:3),c2(0:6);
if(cond)
{
cl=a1*b1;
}
else{
c2=a2*b2;
}
where a1 and b1 are unsigned variables that have 2 bits in total beginning with 0 bit, respectively; c1 is an unsigned variable that has 4 bits in total beginning with 0 bit; a2 and b2 are unsigned variables that have 3 bits in total beginning with 0 bit, respectively; and c2 is an unsigned variable that has 6 bits in total beginning with 0 bit. if(cond) else represents a process for selecting either of c1 or c2, depending on the state specified by the value of cond. While the behavior description above shows an example of a description that performs an operation using unsigned variables, there are also descriptions that perform operations using signed variables.
When carrying out behavior synthesis based on a behavior description similar to the one shown above, conventional circuit synthesizing devices first find operations that are identical to each other but are not used in the same timing in the behavior description, and cause these operations to share the functional unit that are associated with them. Thus, in the behavior description shown above, the operations c1=a1*b1 and c2=a2*b2 are not carried out simultaneously, so a behavior is so synthesized as to carry out a1*b1 and a2*b2 separately, using the same functional unit (i.e., a multiplier).
One example of the results of behavior synthesis according to the procedure described above is shown in FIG. 7.
FIG. 7 shows an example of the results of behavior synthesis that is output from a conventional circuit synthesizing device. In FIG. 7, xe2x80x9cMUXxe2x80x9d represents a multiplexer and xe2x80x9cxc3x97xe2x80x9d a multiplier (i.e., a functional unit).
As shown in FIG. 7, the number of multiplexers for switching variables to be input into a functional unit increases within a behavior-synthesized description. Even so, the area of the synthesized circuit can be reduced, since each multiplexer requires a smaller circuit area than a functional unit.
In conventional circuit synthesizing device, not only functional units but also registers are shared. Register sharing herein means to have one register to hold multiple pieces of data (variables) that are not processed in the same timing.
FIGS. 8 and 9 are data transfer diagrams showing an example of a register sharing method in a conventional circuit synthesizing device conducts. Of these, FIG. 8 is a block diagram showing a register sharing method for signed variables, and FIG. 9 showing a register sharing method for unsigned variables.
FIGS. 8 and 9 show the register sharing method that is conducted when transferring the value of the variable a1 to the register c1 and the value of the variable b1 to the register c2, as follows:
c1=a1;
c2=b1;
Here, the registers c1 and c2 are implemented (i.e., shared) in one register (5 bits).
For example, as shown in FIG. 8, when transferring a1, which is a 2-bit signed variable, and b1, which is a 4-bit signed variable, to a common register (5 bit), bits are added to the variables a1 and b1, respectively, in the numbers that are less than the bit count of the destination register. The multiplexer (MUX) then switches the variable to be transferred to the register, between a1 and b1. Here, since the 0th bit of the variable a1 and that of the variable b1 are signed bits, the same data as the signed bits are inserted in the bits that are in short.
On the other hand, as shown in FIG. 9, for example, when transferring a2, which is a 4-bit unsigned variable, and b2, which is a 2-bit unsigned variable, to a common register (5 bit), bits are added to the variables a2 and b2, respectively, in the numbers that are less than the bit count of the destination register, as with the case above for signed bits. The multiplexer (MUX) then switches the variable to be transferred to the register, between a2 and b2. Here, since neither the variable a2 nor b2 holds a signed bit, data xe2x80x9c0sxe2x80x9d are inserted to the number of bits that are less than the number of bits in the register.
Thus, by conducting sharing for not only functional units but also for registers, a reduction in circuit area can be realized.
Generally, in a conventional circuit synthesizing device as described above, a behavior description is created by employing either operations using signed variables or operations using unsigned variables. However, for cases in which two types of operations, i.e., those using signed variables and those using unsigned variables, exist in the same behavior description, two types of functional units are required, making it impossible to share these functional units.
Thus, conventional circuit synthesizing devices have a drawback that the area of a circuit cannot be minimized in design, since full sharing of functional units and registers are not possible.
An objective of the present invention is to provide a circuit synthesizing device that can synthesize a circuit with a small circuit area by enabling sharing of functional units and registers even when both operations using signed variables and unsigned variables exist, and a method therefor.
Another objective of the present invention is to provide a circuit synthesizing device that can perform simulation of circuit behavior and other processes at a higher speed by using C language for describing hardware in which both operations using signed variables and unsigned variables exist, and a method therefor.
According to the first aspect of the invention, a circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of
re-writing operations using signed variables within the behavior description into operations using unsigned variables, and
based on the re-written behavior description, finding identical operations that do not behave in the same timing and carrying out the process of sharing a functional unit for the variables thus found.
In the preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and operations using signed variables within the behavior description are re-written into operations using unsigned variables according to the translation rules.
In another preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, operations using signed variables are detected from the behavior description, translation rules associated with the detected signed variables are extracted, and the operations using signed variables are re-written into operations using unsigned variables according to the extracted translation rules.
In another preferred construction, when in the operation re-writing process, the operation is multiplication, exclusive-ORs for the signed bits of the signed variables are obtained individually,
when the result of the exclusive-OR operation is 0, the result of multiplication for the variable is output as are, and
when the result of the exclusive-OR operation is 1, a negative sign is added to the result of multiplication for the variable.
In another preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, operations using signed variables are detected from the behavior description, translation rules associated with the detected signed variables are extracted,
when in the operation re-writing process, the operation is multiplication,
exclusive-ORs for the signed bits of the signed variables are obtained individually,
when the result of the exclusive-OR operation is 0, the result of multiplication for the variable is output as are, and
when the result of the exclusive-OR operation is 1, a negative sign is added to the result of multiplication for the variable.
According to the second aspect of the invention, a circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of
finding variables that are not processed in the same timing from the behavior description,
comparing a bit count of the variable to the bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared,
adding same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and then carrying out the process of sharing a register.
According to the third aspect of the invention, a circuit synthesizing method for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising the steps of
re-writing operations using signed variables within the behavior description into operations using unsigned variables, and
based on the re-written behavior description, finding identical operations that do not behave in the same timing and carrying out the process of sharing a functional unit for the variables thus found,
finding variables that are not processed in the same timing from the behavior description,
comparing a bit count of the variable to the bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared,
adding same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and then carrying out the process of sharing a register.
In the preferred construction, translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and the operations using signed variables within the behavior description are re-written into operations using unsigned variables according to the translation rules.
In another preferred construction, xe2x80x9c0sxe2x80x9d are added as the pre-determined data, in the number of bits that is the difference between the number of bits in the unsigned variables and the number of bits in the register, in the case of an unsigned variable.
According to the fourth aspect of the invention, a circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising
re-writing means for re-writing operations using signed variables within the behavior description into operations using unsigned variables, and
means for sharing a functional unit for performing identical operations that do not behave in the same timing from the re-written description.
In the preferred construction, the circuit synthesizing device further comprises translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and
the operation re-writing means re-writes operations using signed variables within the description into operations using unsigned variables according to the translation rules that are stored in the translation table storing means.
In another preferred construction, the circuit synthesizing device further comprises translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance,
the operation re-writing means detects operations using signed variables from the behavior description, extracts translation rules associated with the detected signed variables from the translation table storing means, and re-writes the operations using signed variables into operations using unsigned variables according to the extracted translation rules.
In another preferred construction, the operation re-writing means, when in the operation re-writing process, the operation is multiplication, obtains exclusive-ORs for the signed bits of the signed variables individually, when the result of the exclusive-OR operation is 0, outputs the result of multiplication for the variable as are, and when the result of the exclusive-OR operation is 1, adds a negative sign to the result of multiplication for the variable.
In another preferred construction, the circuit synthesizing device further comprises translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance,
the operation re-writing means detects operations using signed variables from the behavior description, extracts translation rules associated with the detected signed variables from the translation table storing means,
when in the operation re-writing process, the operation is multiplication, obtains exclusive-ORs for the signed bits of the signed variables individually,
when the result of the exclusive-OR operation is 0, outputs the result of multiplication for the variable as are, and when the result of the exclusive-OR operation is 1, adds a negative sign to the result of multiplication for the variable.
According to the fifth aspect of the invention, a circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprises:
means for finding variables that are not processing in the same timing from the behavior description,
means for, comparing a bit count of the variable to the bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared, add the same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and adding predetermined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
means for, after adding data to said variables, carrying out the process of sharing a register.
In the preferred construction, xe2x80x9c0sxe2x80x9d are added as the pre-determined data, in the number of bits that are in short, in the case of an unsigned variable.
According to the sixth aspect of the invention, a circuit synthesizing device for synthesizing a desired circuit from a behavior description indicating the behavior of a design circuit that is created in a hardware description language, comprising
means for re-writing operations using signed variables within the behavior description into operations using unsigned variables,
means for, based on the re-written behavior description, finding identical operations that do no behave in the same timing and carrying out the process of sharing a functional unit for the variables thus found,
means for finding variables that are not processed in the same timing from the behavior description,
means for comparing a bit count of the variable to the bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared,
adding same data as the signed bits, in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
adding pre-determined data, in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register to be shared, and
means for, after adding data to the variables, carrying out the process of sharing a register.
In the preferred construction, the circuit synthesizing device further comprises translation table storing means in which translation rules for re-writing operations using signed variables into operations using unsigned variables are stored in advance, and the operation re-writing means re-writes operations using signed variables within the description into operations using unsigned variables according to the translation rules that are stored in the translation table storing means.
According to a further aspect of the invention, a computer readable memory that records a circuit synthesizing program for synthesizing a circuit from a behavior description indicating the behavior of a circuit that is created by a computer in a hardware description language, wherein the circuit synthesizing program causes the computer to carry out a process of
finding variables that are not processed in the same timing from the behavior description;
comparing a bit count of the variable to the bit count of the register to be shared,
wherein if the bit count of the variable is less than the bit count of the register to be shared,
adding same data as the signed bits in the case of a signed variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and
adding pre-determined data in the case of an unsigned variable, in the number of bits by which the number of bits in the signed variable is less than the number of bits in the register, and then carrying out the process of sharing a register.
According to a further aspect of the invention, a computer readable memory that records a circuit synthesizing program for synthesizing a circuit from a behavior description indicating the behavior of a circuit that is created by a computer in a hardware description language, wherein the circuit synthesizing program causes the computer to carry out the processes of
finding variables that are not processed in the same timing from the behavior description,
when the bit count of the variable is in short when compared with the bit count of the register to be shared,
adding the same data as the signed bits in the number of bits that are in short in the case of a signed variable, and
adding the pre-determined data in the number of bits that are in short in the case of an unsigned variable, and then carrying out the process of sharing a register.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.